Input/Output (I/O) circuits normally operate at a higher voltage level than the core of the integrated circuit (IC). A higher supply level at the I/O pads is desirable to drive huge loads at an optimum speed. A lower supply level at the core enables the use of smaller gate oxide transistors and reduces the power consumption.
FIG. 1 illustrates a conventional level shifter circuit, which receives an input signal at a lower voltage level (VDD) and generates an output signal at a higher voltage level (VDDE). The circuit has two P-channel transistors P1, P2; two N-channel transistors N1, N2 and a standard inverter INV. The transistor P1 is coupled between the VDDE and an OUTA node, its gate is coupled to an OUTB node. The transistor P2 is coupled between the VDDE and the node OUTB, its gate coupled to the OUTA node. The transistor N1 is coupled between the node OUTA and ground GNDE with its gate coupled to the low voltage input signal in. The transistor N2 is coupled between nodes the OUTB and the GNDE, with its gate coupled to receive the signal inn. The signal inn is generated by a low voltage inverting device INV.
The transistors N1, N2, P1, and P2 are typically manufactured using a thicker gate oxide than the transistors comprising the inverting device INV. This thicker oxide enables these to sustain the higher voltage supply (VDDE), while the thinner oxide for INV transistors is enough to sustain the lower voltage supply (VDD).
The circuit of FIG. 1 operates as follows. When the input signal in is at a logic low level (0 Volts), the transistor N1 is off and the transistor N2 is on (because the signal inn is at high logic level (VDD) due to the inverting device INV). As a consequence, the node OUTB is low (0 volts). Thus the P1 is on and the node OUTA is high (VDDE volts). When the input signal in is high (VDD volts), the transistor N1 is on and transistor N2 is off (because the signal inn is low due to the inverting device). Thus the node OUTA is low and the transistor P2 is on due to which the OUTB is high (VDDE volts).
As far as the steady state operation is concerned, the above circuit does not involve any undesirable current consumption as all the voltage levels are well defined. However, when the input signal transits from low to high logic level undesirable current consumption can occur. For instance, let us consider the case when the input signal in rises from a low level to a high level (VDD). When the signal in is low, the nodes OUTA and OUTB are high (VDDE) and low respectively. As the signal in rises above the threshold voltage of the transistor N1, it turns on, thereby trying to pull down the node OUTA. But at this point in time, the transistor P1 is also on. Thus a contention appears between transistors N1 and P1 due to which the node OUTA falls slowly. Eventually, the node OUTA falls sufficiently low to turn on the transistor P2. At this point in time, both transistor N2 and transistor P2 are on and a contention appears between the two due to which the node OUTB rises slowly. As the signal inn goes low, the transistor N2 turns off, thus allowing the transistor P2 to pull up the node OUTB. At some point the node OUTB rises high enough to turn off the transistor P1, thus allowing the transistor N1 to pull down the node OUTA to the GNDE. At this point, the transistor P2 turns fully on and the node OUTB rises to VDDE.
The transistors N1 and N2 have thick gate oxide and hence a higher threshold voltage. Thus if the input signal in is rising, the transistor N1 would turn on later, thus delaying the transitions at nodes OUTA and OUTB. Moreover, if the threshold voltage of N1 is comparable to the lower supply voltage VDD, then the transistor N1 may not get on strongly enough to pull down the node OUTA quickly. Thus, the contention between the transistor N1 and the transistor P1 takes a long time to get resolved, thereby slowing the transition at nodes OUTA and OUTB and consuming a large crowbar current.
FIG. 2 illustrates one approach to solve the above situation arising due to a higher threshold voltage of thicker oxide transistors N1 and N2. This circuit is similar to the circuit of FIG. 1 except that two thick N-channel transistors N7 and N8 are added and the thick gate oxide transistors N1 and N2 are replaced by thin gate oxide transistors for sustaining the low voltage level (VDD). The transistor N7 is added between the transistor N1 and the node OUTA and the transistor N8 is added between the transistor N2 and the node OUTB. The gates of both transistors N7 and N8 are coupled to a reference signal VREF. Both the transistors N7 and N8 are thick gate oxide transistors, which can sustain a higher supply level (VDDE). The VREF is a reference voltage signal, which ensures that transistors N1 and N2 are not stressed by the higher supply VDDE. This VREF signal is generally of the voltage level VDD plus a threshold voltage of thick gate oxide transistor.
As transistors N1 and N2 are thin gate oxide transistors, they have a lower threshold voltage. Thus, if the input signal in is rising, the transistor N1 would get on early, thus causing node A and hence the node OUTA to fall faster. This turns on the transistor P2 which pulls up the node OUTB to turn off the transistor P2, thus activating regenerative feedback and causing rapid transitions at nodes OUTA and OUTB.
There is an inherent drawback in both circuits of FIG. 1 and FIG. 2. To understand this, consider the input signal in switching from a high to low in FIG. 1. Initially when the signal in is high (VDD), the node OUTA is at the ground voltage GNDE and the node OUTB is at higher supply level VDDE. Now as the signal in starts falling, the node OUTA tends to follow due to capacitive coupling between the gate and drain of transistor N1. This causes node OUTA to fall below ground voltage GNDE, thus increasing the overdrive voltage of the transistor P2 and turning it on more strongly. As the signal inn at the gate of the transistor N2 is going high, there is a stronger contention between transistors N2 and P2. As a consequence, the node OUTB falls slowly. Thus the transistor P1 turns on slowly due to, which the node OUTA rises slowly. This further turns off the transistor P2 slowly and hence the fall time at the node OUTB increases. Thus the rise and fall times at nodes OUTA and OUTB increase, thereby making it difficult to operate the circuits of FIG. 1 and FIG. 2 at high frequencies.
A crowbar current is also an important consideration while designing level shifter circuits. It is particularly significant in level shifter circuits which are used to drive heavily loaded I/O pads. When many output signals switch state simultaneously, the crowbar currents of many level shifters get added up to yield an appreciable value for this overall current.
Thus there is a need of a novel level shifter circuit with rapid transitions at the output nodes, hence making high frequency operations possible while consuming a lower crowbar current.